Packaging & Test SEMI Standards Forum (WLP/3D-IC) 2014

Date: Friday , 25 April 2014
Time: 13:00 - 15:00
Venue: Marine Bay Sands Convention & Exhibition, VIP Lounge

Supported by:

3DinCites Logo

 

Industry Standards Efforts to Accelerate Next Generation Packaging and Test

Packaging and Test operations are currently facing major inflection points. 

In Packaging, design houses, foundries, IDMs and OSATs have not agreed upon an industry-wide path toward 3D stacked ICs, delaying high-volume adoption. Consequently, Gartner currently forecasts that TSV devices will account for less than five percent of the units in the total wafer-level packaging market by 2017.Significant standards efforts are underway to address many of the challenges in 3DIC and are bringing together the industry to accelerate stacked IC adoption.Converging and collaborating would strengthen the supply chain and hence bringing down the cost of production in packaging.

In Test, since parallel testing has provides little significant changes in technology, and the next major transition will involve more advanced use of test data utilizing Adaptive Test and other “Big Data” concepts.  This will require unprecedented test data sharing across the supply chain, requiring new industry collaborations and agreements that will require standard data protocols, hierarchies and APIs. 

This forum will introduce and describe the industry-wide standards efforts in 3DIC and Test that will play a major role in facilitating these necessary transitions.

 

Forum Agenda: The intent is to identify area of standards which Singapore and within the region can identify and start forming a Standards committee to gear up for industry and manufacturing readiness.

 

Time: Topic:
13:00 - 13:20

3D IC Standards Overview

 

3D IC Standards Status

a) Thin wafer handlimg

b) TSV Inspection and metrology

c) 3D IC wafer bonding

13:20 - 15:00

Forum Discussion:

- In Situ Interposer testing
- Partial stack testing
- 3D stack alignment strategy   

(front side, backside marking)
- Assembly flow D2D, D2W

 




 

 

 

 

 

Chaired by: Ms E. Jan Vardaman and Dr Timothy G.Lenihan (TechSearch International, Inc)

Event Coverage by: Ms Francoise Von Trapp (3D InCites)

Panelist: 

Mr James Amano (SEMI International Standards)

Dr. Surya Bhattacharya (A*STAR Institute of Microelectronics)

Dr Surasit Chungpaiboonpatana (NXP-PHILIPS)

Dr. Yoon Seung Wook (STATS chipPAC)

Mr. Jeff Lin (United Microelectronics Corp)

Mr. Li Keong  (United Microelectronics Corp)

Dr Jeffrey Lam (Globalfoundries)

Mr Alapati Ramakanth (Globalfoundries)

Dr Lou Choon Leong (STAr Technologies)

Mr Vincent Tong (Xilinx)

 

For interested parties, please email your details to Ms Shannen Koh (skoh@semi.org)